Mmio addressing using a translation table

ABSTRACT

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

BACKGROUND

The present disclosure relates to the field of computer systems. More particularly, the present disclosure relates to processing an instruction by a processor.

When processing instructions by a processor, often communication with peripheral devices, e.g., input/output devices or memory devices, is required. Such communication may require an identification of the target device and/or addresses assigned to the target device. Different methods for enabling such a communication are known. Considering modern computer systems, the communication with peripheral devices gets more and more time critical. With computer systems becoming more and more complex, the complexity often comes with low efficiency regarding the required communication when executing instructions.

SUMMARY

Various embodiments provide a method for processing an instruction by a processor as well as a computer system and a computer program product for executing the method as described by the subject matter of the independent claims. Advantageous embodiments are described in the dependent claims. Embodiments of the present invention can be freely combined with each other if they are not mutually exclusive.

In one aspect, the disclosure relates to a method for processing an instruction by a processor. The processor is operationally connected to one or more buses. The processor determines the instruction is to access an address of an address space. The address space maps a memory and additionally comprises a range of MMIO addresses. The method determines the address being accessed by the instruction is within the range of MMIO addresses. The method translates, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

In a further aspect, the invention relates to a computer system. The computer system comprises one or more processors and a memory communicatively coupled to the one or more processors. The processor is operationally connected to one or more buses. The computer system is configured to process an instruction by a processor. The system determines the instruction is to access an address of an address space. The address space maps a memory and in addition comprises a range of MMIO addresses. The processing of the instruction comprises determining whether the address being accessed by the instruction is comprised by the range of MMIO addresses. The system translates, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus using a translation table. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

In a further aspect, the disclosure relates to a computer program product. The computer program product comprises a computer-readable storage medium which has machine executable program instructions embodied therewith. The computer program product is configured to process an instruction by a processor. The computer program product determines the instruction is to access an address of an address space. The address space maps a memory and additionally comprises a range of MMIO addresses. The computer program product determines the address being accessed by the further instruction is within the range of MMIO addresses. Based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed is translated using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the further instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure.

FIG. 1 depicts a block diagram of an example computer system, in accordance with embodiments of the present disclosure.

FIG. 2 depicts a schematic diagram of an example address structure, in accordance with embodiments of the present disclosure.

FIG. 3 depicts a schematic flow diagram of an example method for processing an instruction accessing an address of an address space, in accordance with embodiments of the present disclosure.

FIG. 4 depicts a schematic flow diagram of an example method, in accordance with embodiments of the present disclosure.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION

The descriptions of the various embodiments of the present invention are being presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

A MMIO (Memory Mapped Input/Output) address is an address used by processor instructions to read or write on a bus, such as e.g., a PCIe (Peripheral Component Interconnect Express) bus, in a memory mapped way. As used herein, memory mapped means that the processor instructions use the same addressing scheme as used for accessing physical main memory. For example, an instruction with store-to-memory characteristics may send the data referred to through a PCIe bus to a PCIe device instead of storing the respective data to memory, and an instruction with load characteristics may request a device, like e.g., an I/O device, through the PCIe bus to respond with the requested data instead of reading the data from memory.

Embodiments of the present disclosure discussed herein are presented where the buses are PCIe buses, the device is a PCIe device, and the bus address is a PCIe bus address. However, the present disclosure should not be read as limited to such and may be used with or adapted to alternate buses, devices, and bus addresses.

PCIe addresses are generally organized in a hierarchical addressing structure. A BAR (Base Address Register) in PCIe defines a start address and length of an address space assigned to a component, e.g., a function, a switch, a bus, a PCIe bus unit, etc. Firmware typically initializes the addressing structure by executing a bus walk, i.e. systematically scanning or “walking through” the components accessible via the buses comprised by the computer system.

Some embodiments of the present disclosure have the beneficial effects of simplifying and speeding up device identification, and more particularly, identification of a bus and bus address assigned to a respective device. A translation table may provide a simple approach to translate a MMIO address to a bus identifier and a bus address. The device may for example be an input/output (I/O) device or a memory device. Embodiments may introduce an MMIO range between a Memory Management Unit (MMU) of a processor and a dynamic address translation table of an operating system on one side and one or more PCIe Base Address Registers (PCIe BAR) on the other side.

FIG. 1 depicts a computer system 100 suited for implementing a method for processing an instruction accessing a MMIO address and translating the MMIO address in order to determine a bus identifier and a bus address to which a request is to be sent based on the instruction processed. It will be appreciated that the methods described herein are at least partly non-interactive, and automated by way of computerized systems, such as servers or embedded systems. In example embodiments though, the methods described herein may be implemented in a (partly) interactive system. These methods may further be implemented in software (e.g. instructions 112), firmware (including basic input output system (BIOS) 122), hardware (e.g., processor 105), or a combination thereof. In example embodiments, the methods described herein are implemented in software, as an executable program, and are executed by a special or general-purpose digital computer, such as a personal computer, workstation, minicomputer, or mainframe computer. The most general computer system 100 therefore includes a general-purpose computer 101.

In example embodiments, in terms of hardware architecture, as shown in FIG. 1, the computer 101 includes a processor 105, memory (e.g., main memory) 110 coupled to a memory controller 115, and one or more input and/or output (I/O) devices (or peripherals) 10 and 145 that are communicatively coupled via a local input/output controller 135. The input/output controller 135 may be, but is not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller 135 may have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components. The I/O devices 10 and 145 may e.g., comprise any portable storage device 10 or stationary storage device 145.

The processor 105 is a hardware device for executing software, particularly that stored in memory 110. The processor 105 may be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer 101, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing software instructions.

The memory 110 may include any one or combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM). Note that the memory 110 may have a distributed architecture, where various components are situated remote from one another, but may be accessed by the processor 105.

The software in memory 110 may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions, notably functions involved in embodiments of this disclosure. In the example of FIG. 1, software in the memory 110 includes instructions 112.

The software in memory 110 may also include a suitable operating system (OS) 111. The OS 111 essentially controls the execution of other computer programs, such as instructions 112 for implementing methods as described herein.

The methods described herein may be in the form of a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When being provided as a source program, then the respective program needs to be translated via a compiler, assembler, interpreter, or the like, which may or may not be included within the memory 110, so as to operate properly in connection with the OS 111. Furthermore, the methods may be written as an object-oriented programming language, which has classes of data and methods, or a procedure programming language, which has routines, subroutines, and/or functions.

In example embodiments, a conventional keyboard 150 and mouse 155 may also be coupled to the input/output controller 135. Other output devices such as the I/O devices 145 may include input devices, for example but not limited to a printer, a scanner, microphone, and the like. Finally, the I/O devices 10 and 145 may further include devices that communicate both inputs and outputs, for instance but not limited to, a network interface card (NIC) or modulator/demodulator (for accessing other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, and the like. The I/O devices 10 and 145 may be any generalized cryptographic card or smart card known in the art. The system 100 may further include a display controller 125 coupled to a display 130. In example embodiments, the system 100 may further include a network interface for coupling to a network 165. The network 165 may be an IP-based network for communication between the computer 101 and any external server, client and the like via a broadband or other connection. The network 165 transmits and receives data between the computer 101 and external systems 30. In example embodiments, network 165 may be a managed IP network administered by a service provider. The network 165 may be implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as WiFi, WiMax, etc. The network 165 may also be a packet-switched network such as a local area network, wide area network, metropolitan area network, Internet network, or other similar type of network environment. The network 165 may be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

If the computer 101 is a PC, workstation, intelligent device or the like, the software in the memory 110 may further include a basic input output system (BIOS) 122. The BIOS is a set of essential software routines that initialize and test hardware at startup, start the OS 111, and support the transfer of data among the hardware devices. The BIOS is stored in ROM so that the BIOS may be executed when the computer 101 is activated.

When the computer 101 is in operation, the processor 105 is configured to execute instructions 112 stored within the memory 110, to communicate data to and from the memory 110, and to generally control operations of the computer 101 pursuant to the software. The methods described herein and the OS 111, in whole or in part, but typically the latter, are read by the processor 105, possibly buffered within the processor 105, and then executed.

When the systems and methods described herein are implemented in instructions 112, as is shown in FIG. 1, the methods may be stored on any computer readable medium, such as storage 120, for use by or in connection with any computer related system or method. The storage 120 may comprise a disk storage such as HDD storage.

FIG. 2 depicts a schematic diagram illustrating an example address structure. An address space may be provided in form of a partition absolute address space 203 assigned to a partition. When the partition issues an instruction, the instruction may access a virtual address 200. The virtual address may be translated using a Memory Management Unit (MMU) and/or Dynamic Address Translation (DAT) table 202 to a partition absolute address of the partition absolute address space 203. For example, the virtual address may be converted by DAT to a real address and then by prefixing to an absolute address. The partition absolute address space 203 may comprise a range of absolute addresses mapping a memory. The respective range may extend from a lower limit, e.g., 0, to an upper limit MLS. In addition, the partition absolute address space 203 comprises a range of MMIO addresses extending from a lower limit, i.e. start like e.g., 0xF0 . . . , to an upper limit, i.e. end like e.g., 0xFFFFFFFFFFFFFFFF. The absolute address accessed by the instruction may either be comprised by the memory mapped range 204 or by the MMIO range 206 of absolute partition addresses. The MMIO range 206 may cover BARs of one or more PCIe bus units (PBU) 210 and 208. For example, absolute addresses 0xF1 . . . to 0xF2 . . . may be addresses for accessing a first PBU0 BAR 208, while other absolute partition addresses 0xF0 . . . to 0xF1 . . . may be addresses for accessing a further PBU1 BAR 210. The PBUs may comprise one or more buses. Thus, the PBU Bars may comprise one or more bus BARs. For example, PBU0 BAR 208 may comprise BusO Bar 212. BusO Bar 212 may e.g., comprise SwitchO Portl BAR 214 which is accessible via a range of absolute partition addresses, like e.g., 0xF10 . . . to 0xF11 . . . . SwitchO Portl BAR 214 may comprise one or more function BARs, like e.g., Func 1 BAR 216 and Func 2 BAR 218, each of which is addressable via range of absolute partition addresses comprised by the MMIO range 206. Func 1 BAR 216 may e.g., be addressable using absolute partition addresses 0xF1010 . . . to 0xF1011 . . . and Func 2 BAR 218 may e.g., be addressable using absolute partition addresses 0xF1011 . . . and 0xF1012 . . . . Thus, a MMIO address comprised by MMIO range 206 may be translated to a bus identifier identifying a bus, like e.g., BusO, and a bus address, e.g., a PCIe bus address. The PCIe bus address may identify a PCIe bus address of a PCIe bus address space assigned to the identified bus, e.g., BusO.

FIG. 3 depicts a schematic flow diagram of an example method 300 for processing an instruction accessing an address of an address space. At 310, a processor receives the instruction accessing an address of an address space. The address can be a partition absolute address (PAA) 330 of a partition absolute address space. PAA 330 may comprise a first section providing a MMIO index (MMIO_Idx) 332, which may be used to identify an entry 338 of the translation table providing a bus identifier Hardware Request Routing Address (HRRA) 340, and a remaining portion 334.

At 312, in order to identify entry 308 of the translation table, the processor multiplies the MMIO_Idx with a byte offset. The byte offset may e.g., be 16 bytes (where the *16 in FIG. 3 represents multiplication by 16).

At 314, the processor adds a MMIO table base address. The result may be the address of translation table entry 338. Entry 338 may comprise a bus identifier HRRA 340 identifying a bus. HRRA 340 may e.g., identify a drawer, cluster, port etc. The entry 338 may further comprise a base address (MMIO_base) 344 of the identified bus, i.e. a lower limit of the bus address space assigned to the identified bus, as well as a limit address (MMIO_limit) 342 of the identified bus, i.e. an upper limit of the bus address space assigned to the identified bus.

At 316, the remaining portion 334 of PAA 330 may e.g., be added to MMIO_base by the processor.

At 318, the processor checks whether the resulting bus address is within the bus address space assigned to the identified bus. In other words, the processor checks whether the result is smaller than MMIO_limit 342. In response to determining that the result is not smaller, the bus address is erroneous and lies without the bus address space assigned to the identified bus and e.g., a machine check may be performed at 320. In response to determining that the result is smaller, the bus address is a valid bus address of the bus address space assigned to the identified bus and a request is forwarded to the PBU identified by HRRA 310 at 322. More precisely, a request directed to a device accessible via the identified bus is sent via the identified bus to the bus address in step 322.

FIG. 4 depicts a schematic flow diagram of an example method 499 for processing an instruction accessing a partition absolute address. At 400, the partition absolute address is accessed by the instruction. At 402, it is determined whether the PAA is an MMIO address (MMIOA), i.e. whether the PAA is comprised by the MMIO range. If this is not the case, the PAA may be an address mapping an address of a memory. Thus, at 404, the memory is accessed. If it is the case that it is an MMIOA, the MMIOA provided in form of the PAA is translated at 406 using the translation table (TT) in order to provide the bus identifier and the bus address. At 408, a request is sent to the translation result of 406.

It is understood that one or more of the aforementioned embodiments of the invention may be combined as long as the combined embodiments are not mutually exclusive. Ordinal numbers, like e.g., ‘first’ and ‘second’, are used herein to indicate different elements assigned with the same name, but do not necessarily establish any order of the respective elements.

According to some embodiments, the address space comprising the address accessed by the instruction is an absolute partition address space assigned to a partition. Furthermore, the translation table is assigned to the partition and the instruction is an instruction issued by the partition. Embodiments may have the beneficial effect of providing partition individual translation tables. Thus, e.g., different access rights may be defined for different partitions.

According to some embodiments, the processor can be provided with a partition identifier identifying the partition issuing the instruction. Embodiments may have the beneficial effect of that the processor is enabled to identify which partition is issuing the instruction and thus trying to access the MMIO address and via the MMIO address, the underlying bus and bus address. The partition identifier may e.g., be used to identify a translation table assigned to the respective partition.

According to some embodiments, the translation table provides translations for each address of the MMIO range and to each address of the MMIO range an access indicator is assigned. The access indicator indicates, whether an access to the respective address of the MMIO range is allowed. The processor uses the access indicator to check whether the access the address being accessed by the instruction is allowed. In case the access is not allowed, the processor prevents that a request based on the instruction is sent. Embodiments may have the beneficial effect that all MMIO addresses are visible for a partition, but that using the access indicator access rights may be defined, restricting the access rights of the respective partition.

According to some embodiments, in order to prevent that a request based on the instruction is sent, when the access is not allowed, the processor may interrupt the processing of the instruction, and a pending interrupt may be generated, or the instruction may be ignored by the processor. Furthermore, an exception may be indicated by the processor.

According to some embodiments, the translation table only provides translations for addresses of the MMIO range that the partition is allowed to access. Embodiments may have the beneficial effect that translations are only provided for MMIO address which the partition is allowed to access. For other MMIO addresses, no translations are provided. In such embodiments, the processor is unable to send a request directed to the device based on an instruction trying to access such an MMIO address.

According to some embodiments, when the translation table provides no translation for the address being accessed by the instruction, no request based on the instruction is sent.

According to some embodiments, the processor determines whether the bus address resulting from the translation lies within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation. According to some embodiments, in case the bus address resulting from the translation does not lie within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation, the processor prevents that a request based on the instruction is sent. Embodiments may have the beneficial effect of ensuring that the bus address resulting from the translation lies within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation. In these embodiments, only if this is the case, a request directed to the device is sent via the identified bus to the bus address. Otherwise, the MMIO address used may be erroneous. Thus, using an erroneous MMIO address is prevented which otherwise could result in sending a request to a wrong device.

According to some embodiments, the translation table comprises identifiers identifying an upper and a lower limit of the bus address space assigned to the bus identified by the bus identifier resulting from the translation. The identifiers identifying the upper and the lower limit of the bus address space are used for determining whether the resulting bus address lies within the range defined by the upper and the lower limit. Embodiments may have the beneficial effect of providing an efficient approach to determine whether the bus address resulting from the translation lies within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation.

According to some embodiments, the address being accessed by an instruction comprises a first section encoding an identifier for identifying the bus identifier. According to some embodiments, the identifier for identifying the bus identifier comprises an entry identifier identifying an entry in the translation table providing the bus identifier. Embodiments may have the beneficial effect of efficiently providing the bus identifier. According to some embodiments, the address comprises a second section encoding the bus address of the bus address space assigned to the device accessible via the bus identified by the first section.

According to some embodiments, write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests. As used herein, write combine refers to a computer bus technique for allowing data to be combined and temporarily stored in the aggregation buffer to be released together later in burst mode. Embodiments may have the beneficial effect of providing an efficient approach to execute a plurality of write instructions.

According to some embodiments, for each combination of bus identifier and bus address, two addresses are provided in the MMIO range. A first address is provided for executing a write through to the respective bus address, while a second address is provided for executing a write combine to the respective bus address. Embodiments may have the beneficial effect of efficiently implementing a write through mode as well as a parallel write combine mode. Depending on the MMIO address accessed, it may be chosen between the write through mode and the write combine mode. For example, a write combining enabled bit may be added to the MMIO address range for controlling aggregation/ordering. For example, an unused bit may be considered, e.g., bit 1. Thus, each bus address may be seen as mapped twice into the MMIO address range, once with write combined ordering and once with write through ordering.

According to some embodiments, the bus identifier comprises one or more of the following for identifying the bus: a node number, a chip number, a bus unit number, or a bus number. Embodiments may have the beneficial effect of providing an efficient bus identifier.

According to some embodiments, an MMIO capability bit is added to a query function for an operating system (OS) to identify if the system supports the embodiments of the present disclosure discussed herein. If the capability bit is set, the firmware may configure BAR spaces in PCIe devices to contain proper physical addresses (PAs) before signaling hot plug to the OS. Furthermore, the OS may be configured to actually use these PAs.

According to some embodiments, the computer system further is configured to execute any of the embodiments of the method for processing the instruction by the processor as described herein.

The present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 

What is claimed is:
 1. A method for processing an instruction by a processor, wherein the processor is operationally connected to one or more buses, wherein the method comprises: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.
 2. The method of claim 1, wherein the buses are PCIe (Peripheral Component Interconnect Express) buses, wherein the device is a PCIe device, and wherein the bus address is a PCIe bus address.
 3. The method of claim 1, wherein the address space comprising the address accessed by the instruction is an absolute partition address space assigned to a partition, wherein the translation table is assigned to the partition, and wherein the instruction is an instruction issued by the partition.
 4. The method of claim 3, further comprising: receiving, by the processor, a partition identifier identifying the partition issuing the instruction.
 5. The method of claim 3, wherein the translation table contains translations for each address of the MMIO range, wherein each address of the MMIO range has an assigned access indicator which indicates whether an access to the respective address of the MMIO range is allowed.
 6. The method of claim 3, wherein the translation table only contains translations for addresses of the MMIO range the partition is allowed to access.
 7. The method of claim 1, further comprising: determining, whether the bus address resulting from the translation lies within the range of the bus address space assigned to the bus identified by the bus identifier resulting from the translation.
 8. The method of claim 7, wherein the translation table comprises identifiers identifying an upper limit and a lower limit of the bus address space assigned to the bus identified by the bus identifier resulting from the translation for determining whether the resulting bus address lies within the range defined by the upper and a lower limit.
 9. The method of claim 1, wherein the address being accessed by the instruction comprises a first section encoding an identifier for identifying the bus identifier.
 10. The method of claim 9, wherein the identifier for identifying the bus identifier comprises an entry identifier identifying an entry in the translation table providing the bus identifier.
 11. The method of claim 9, wherein the address comprises a second section encoding the bus address of the bus address space assigned to the device accessible via the bus identified by the first section.
 12. The method of claim 1, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests.
 13. The method of claim 12, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address.
 14. The method of claim 1, wherein the bus identifier comprises one or more of the following for identifying the bus: a node number, a chip number, a bus unit number, and a bus number.
 15. A system for processing an instruction by a processor comprising: one or more processors, wherein the one or more processors are operationally connected to one or more buses; and a memory communicatively coupled to the one or more processors, wherein the memory comprises instructions which, when executed by the one or more processors, cause the one or more processors to perform a method comprising: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.
 16. The system of claim 15, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests.
 17. The system of claim 16, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address.
 18. A computer program product for processing an instruction by a processor, the computer program product comprising a computer readable storage medium having machine executable program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a computer to perform a method comprising: determining the instruction is to access an address of an address space, wherein the address space maps a memory, and wherein the address space additionally comprises a range of Memory Mapped Input/Output (MMIO) addresses; determining the address being accessed by the instruction is within the range of MMIO addresses; translating, based on the determination that the address being accessed is within the range of MMIO addresses, the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space assigned to the identified bus, using a translation table, wherein the bus address resulting from the translation is assigned to a device accessible via the identified bus; and sending, based on the instruction, a request directed to the device via the identified bus to the bus address resulting from the translation.
 19. The computer program product of claim 18, wherein write combine is enabled for the addresses of the MMIO range using an aggregation buffer for aggregating requests.
 20. The computer program product of claim 19, wherein for each combination of bus identifier and bus address, two addresses are provided in the MMIO range, wherein a first one of the two addresses is provided for executing a write through to the respective bus address and a second one of the two addresses is provided for executing a write combine to the respective bus address. 